1. Field of the Invention
The present invention relates to packaging substrate structures, and more particularly, to a packaging substrate having a heat-dissipating structure.
2. Description of the Prior Art
Owing to development of semiconductor packaging technology, semiconductor packages nowadays come in a variety of forms. Known methods for packaging semiconductor devices involve mounting an integrated circuit-laden semiconductor chip on a packaging substrate or a lead frame, electrically connecting the semiconductor chip to the packaging substrate or the lead frame, and encapsulating the packaging substrate with encapsulant. Ball Grid Array (BGA), which represents an advanced semiconductor packaging technology, is characterized by mounting a semiconductor chip on a packaging substrate and implanting a plurality of solder balls aligned in an array on the back of the packaging substrate, thereby increasing I/O connections provided on a carrier for the semiconductor chip per unit area so as to meet the demand for high-integration semiconductor chips. Ball Grid Array features solder balls whereby a BGA package unit is capable of being electrically connected to an external device via the solder balls.
Known semiconductor package structures are packaged in the following ways. Semiconductor chips are attached by inactive surfaces thereof, one by one, to the top surface of a substrate by wire bonding. The alternative, flip-chip packaging, is to implant solder bumps on the electrode pads of active surfaces of the semiconductor chips so as to allow the semiconductor chips to be mounted by the active surfaces on the substrate, and then implant solder balls on the back of the substrate so as to allow the semiconductor chips to be electrically connected to an external device. The prior art achieves a high pin number and yet is flawed by a resultant intricate layout on an unfavorably thick package structure due to limitation of semiconductor chips in surface area and size. Hence, the prior art is hardly conducive to miniaturization and improvement in performance as far as semiconductor chip package structures are concerned.
Given the boom of the electronic industry, the trend of the development of electronic products is toward versatility and high performance. To meet the demand for integration and miniaturization of semiconductor packages, manufacturers have to embed a semiconductor chip in a packaging substrate at the cost of the following drawback. An increasingly great amount of heat is generated by semiconductor chips in operation; procrastinated or inefficient dissipation of heat generated by the semiconductor chips in operation result in deteriorated performance and shortened service life of the semiconductor chips.
FIG. 1 is a cross-sectional view of a conventional package structure for a semiconductor chip embedded in a substrate. As shown in the drawing, a package structure comprises: a heat-dissipating board 12 formed with a cavity 120 therein; a semiconductor chip 13 with an active surface 13a having a plurality of electrode pads 131 formed thereon and an opposite inactive surface 13b, wherein the semiconductor chip 13 is received in the cavity 120 by the inactive surface 13b; a dielectric layer 14 formed on the heat-dissipating board 12 and the active surface 13a of the semiconductor chip 13; and a wiring layer 15 formed on the dielectric layer 14 and electrically connected to electrode pads 131 of the semiconductor chip 13 by conductive vias 151 formed in the dielectric layer 14.
Although the aforesaid drawback of the prior art can be overcome with a solution, namely using a package structure which comprises a semiconductor chip-embedded substrate, the solution brings more problems. Given a significant difference between the heat-dissipating board 12 and the dielectric layer 14 in coefficient of thermal expansion (CTE), variable thermal stress exhibited by individual components, together with unilateral build-up, is likely to cause warpage to the package structure. Uncontrolled warpage may delaminate a package structure or crack a long-compressed semiconductor chip. In this regard, a way to prevent warpage is to thicken a heat-dissipating board so as to counter the thermal stress developed in a substrate due to variation of temperature. However, a thick heat-dissipating board accompanies a thick bulky package structure and incurs process costs.
Accordingly, an issue that prevails in the electronic industry and calls for immediate solution involves providing a packaging substrate structure for elimination of the drawbacks of the prior art, namely warpage, increased thickness and weight, and high costs.